The fabrication of very large scale and ultra large scale integrated circuits with line widths in the sub-micron region is placing increasing demands on processes such as metallization. Metal interconnections within the circuits not only need to have a pitch commensurate with the small geometries inherent in highly packed integrate systems but also must make electrical contact to underlying metal or doped semiconductor layers through small "high aspect ratio" contact or "via" holes. Contact or via formation in small line-width circuits is currently a major problem that must be solved to allow microelectronics technology to progress to higher packing densities. It is a problem that is painfully evident in current silicon integrated circuit fabrication. Current methods of via filling lead to process-induced irregularaties which in turn disrupt the electrical continuity of the connection in the contact hole. See "Low Pressure Chemical Vapor Deposition of Tungsten and Aluminum for VLSI Applications", by R. A. Levy and M. L. Green, in "Materials Issues in Silicon Integrated Circuit Processing", Editors Mark Whitmer, James Stimmel, Michael Strathman, Materials Research Society Symposia Proceedings, Vol. 71, Apr. 15-18, 1986 and "Interconnections in VLSI", by Prabhakar B. Ghate, in Physics Today, October 1986.
Metallization is recognized as one of the the most critical processes in the fabrication of high density integrated circuits. The final level (or levels) of metal interconnect devices such as resistors, transistors, and capacitors and also connect various sections of the circuit together to form the final integrated system. The trend in MOS and bipolar integrated circuits has been toward higher levels of integration. The accompanying increase in component packing density has led to decreasing lateral and vertical dimensions within the devices and circuits. The metal lines which form the interconnections have become narrower to facilitate smaller pitch so that more wiring may be run in a smaller area. The contact holes and vias also have to be reduced to a similar scale to maintain the reduced pitch.
The contact holes not only are small, e.g., 0.5 micron across, but are formed by highly anisotropic etching (usually reactive ion etching). Steep sidewalls have the effect of maintaining a large contact area at the base of the via without making the top of the hole unacceptably large. Unfortunately, since the operating voltages of the integrated circuits have generally not been reduced (due to system considerations), the field oxide dielectric thicknesses cannot be reduced, and remain at about 0.5 to 1.0 micron. The depth-to-width aspect ratios of the nearly vertical walled via contact holes tend to be high, typically from 1 to 2.
Much work has been done on the electrical properties of reduced area contacts, specifically with reference to the resistance and reliability of the electrical contact to an underlying doped semiconductor region or to a previously deposited metal layer. However, non-uniformity of metal film thickness within the contact holes causes unreliable electrical contact through vias.
Aluminum commonly is used as a final or top level metal interconnection material and commonly is deposited by evaporation or sputtering. However, these techniques promote non-uniform metal deposition on topographical features (edges) in the underlying dielectric. The large arrival angle for the depositing metal at the top edges of features such as steps, combined with the low surface mobility of the adsorbed material, allows a thicker film of metal to form, typically up to 1.5 times the thickness of the metal film at a "flat" site on the substrate. The metal film then projects beyond the edge of the feature. This creates a problem for small geometry contact holes, because the "shadowing" effect of the projecting metal film at the top edge of the hole, combined with the small arrival angle at the bottom of the step, excludes sufficient metal deposition within the base and sides of the hole, resulting in poor electrical continuity.
The formation of metal films for interconnection layers by chemical vapor deposition (CVD) is a viable alternative to evaporation or sputtering. CVD processes are considerably more conformal over steps, and therefore should be more suitable for small geometry circuit fabrication. Aluminum or refractory metal films (e.g., tungsten) may be deposited by this method. CVD involves the pyrolytic decomposition of a vapor or gas containing the metal to be deposited on the surface of the substrate, which is heated by resistive heating elements, rf energy, or incoherent light. Low pressure CVD (LPCVD) involves deposition at low pressures and temperatures and the apparatus used can be relatively uncomplicated (i.e., a heated tube) compared to an atmospheric pressure system that relies on strict control of hydrodynamic aspects. The deposition reaction is generally heterogeneous and generally includes the following steps: 1) diffusion of reactants to the surface, 2) adsorption of the reactants at the surface, 3) surface events (e.g., chemical reaction, surface diffusion), 4) desorption of products from the surface, and 5) diffusion of products away from the surface.
In the case of tungsten deposition, the reactants commonly are tungsten hexafluoride in a hydrogen carrier, and the product is hydrogen fluoride HF. For aluminum deposition, the reactant is an organometallic such as triisobutyl aluminum (TIBA) and the products are various hydrocarbons.
Since the reaction steps in CVD are sequential, the slowest step largely governs the total deposition rate. Diffusion of the reactants to the surface can be the limiting step in atmospheric pressure CVD but does not tend to be a limitation at low pressures, since diffusion then is considerably more rapid. However, film formation at reduced pressure also means that the deposition rate can be considerably smaller as the partial pressure of reactant, and hence the amount (density) of metal containing species, is lower. The reactant gas pressure is chosen to maintain a reasonable deposition rate.
In the case of blanket film deposition of thick (i.e., greater than 0.5 micron) metal layers, non-uniform film formation still can occur on the edges of steep steps with CVD. If the deposition pressure is increased to increase deposition rates, or if the reaction temperature is reduced to avoid gas phase reactions, the film will begin to deposit non-conformally. The net effect is, as in the case of evaporation and sputtering, a thicker film surrounding the top of the step. This is not normally a great problem for CVD metallization unless the step is a small, high aspect ratio via hole. In this case the hole is gradually closed off, which interferes with transport of reactants to the base of the hole. Hence, the contact hole may be inadequately filled by the metal. For example, FIG. 1A shows a via hole 4 in an oxide layer 3 formed on a silicon substrate 2 of a wafer 1. FIG. 1A shows how via hole 4 is filled during a typical deposition of an aluminum layer 6 on the upper surface of field oxide 3. Metal preferentially is deposited on the upper edge of the via step 4, forming shoulders 7A that tend to close off lower portions of the via hole. Insufficient aluminum is deposited to completely fill the lower portions of the via hole. The result is formation of voids in the via and thinned metal film on the lower portion of the via hole walls, resulting in inadequate electrical contact to the metal 6A deposited on the substrate 2 (or doped region or previously deposited metal thereon) at the bottom of via hole 4.
It is clear that an alternative method of metallizing small geometry contact holes is necessary to ensure adequate metal deposition within via holes and thereby preserve reliable electrical continuity. The way this may be achieved is to selectively or preferentially deposit metal in the holes without creating a "barrier" at the top of the hole for further deposition. Selective thermal CVD methods currently available allow selective deposition of materials such as tungsten in the contact holes but these rely on surface effects unique to the reactants, wafer surface, and system used. The reactants (WF.sub.6 /H.sub.2) do not decompose to deposit tungsten on the oxide surface but do react on bare silicon, silicide, or metal. The mechanism for this is not well understood, but is thought to be due to the fact that silicon atoms in the silicon dioxide are not available for the initial reduction of the reactant.
The main drawbacks of these selective CVD methods are: (1) tungsten will deposit on irregularities, randomly distributed sites which allow a reduction of the tungsten hexafluoride reactant, on the surface of the oxide to form particles, and (2) lateral encroachment of metal due to silicon consumption occurs on the surface of the silicon at the base of the contact, and severely limits the minimum spacing of contact structures. While these effects may be tolerable for present geometry sizes, problems could be encountered due to contamination by the metal particulates or disruption of underlying shallow junctions after silicon consumption in smaller submicron circuit technologies. Similar selective CVD methods do not exist for aluminum, since blanket film formation occurs. Deposition cannot be made selective by utilizing surface reaction conditions as in the case of tungsten, because the aluminum readily deposits on silicon or silicon dioxide. This is one of the reasons why tungsten is being favored in new VLSI metallization schemes. See "Properties of Chemically Vapor-Deposited Tungsten Thin Films on Silicon Wafers", by Michael Diem, Michael Fisk and John Goldman, in "Thin Solid Films", Vol. 107, Pages 39-43 (1983) and "Laser-Induced Chemical Vapor Deposition" by D. Bauerle, in "Laser Processing and Diagnostics", D. Bauerle, Editor, Pages 166-182, and "Laser Fabrication of Integrated Circuits" by Irving P. Herman, in "Laser Processing and Diagnostics", D. Bauerle, Editor, pages 396-416.